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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 9. Serial Input Address and Configuration Bit Map
RESET
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
Note: testmode address used only by FSL is D[15:11]=01111 with RST voltage higher than 8.0 V typ.
ADDRESS 00000 — Initialization
The Initialization register is used to read the various
statuses, choose one of the six outputs current recopy,
enable the STOP pin, and synchronize the switching phases
between different corner light devices. The register bits D1
and D0 determine the content of the 16 bits of SO data.
(Refer to the section entitled Serial Output Communication
(Device Status Return Data) ) Bits D9 : D2 are described in
Table .
Table 10. Initialization Register
SI Address
The watchdog timeout is specified by the t WDTO
parameter. As long as the WD bit (D10) of an incoming SPI
message is toggled within the minimum watchdog timeout
period (WDTO), the device will operate normally. If an
internal watchdog timeout occurs before the WD bit is
toggled, the device will revert to Fail mode. All registers are
cleared. To exit the Fail mode, send valid SPI communication
with WD bit = 1.
SI Data
D15
0
D14
0
D13
0
D12
0
D11
0
D10
WD
D9
0
D8
0
D7
STOPen
D6
PWM
sync
D5
0
D4
MUX2
D3
MUX1
D2
MUX0
D1
SOA1
D0
SOA0
x = Don’t care
D6 (PWM sync) = 0, No synchronization
D6 (PWM sync) = 1, Synchronization on CSB positive edge
D7 (STOPen) = 0, STOP pin does not control the output 4.
D7 (STOPen) = 1, STOP pin controls the output 4.
ADDRESS 00001 — Configuration OL
The Configuration OL register is used to enable the open
load detection for LEDs in Normal mode (OLLEDn in Table 9 )
and to active the LED Control.
When bit D0 is set to logic [1], the open load detection
circuit for LED is activated for output 1. When bit D0 is set to
logic [0], open load detection circuit for standard bulbs is
activated for output 1.
When bit D5 is set to logic [1], the LED Control is activated
for output 1.
D4, D3, D2 (MUX2, MUX1, MUX0) = 000, No current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 001, OUT1 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 010,current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 011, OUT3 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 100, OUT4 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 101, OUT5 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 110, External Switch current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 111, Temperature analog
feedback
ADDRESS 00010 — CONFIGURATION PRESCALER
AND SR
Two configuration registers are available at this address.
The Configuration Prescaler when D9 bit is set to logic [0] and
Configuration SR when D9 bit is set to logic [1].
The Configuration Prescaler register is used to enable the
PWM clock prescaler per output. When the corresponding
PR bit is set to logic [1], the clock prescaler (reference clock
divided by 2) is activated for the dedicated output.
The SR Prescaler register is used to increase the output
slew-rate by a factor of 2. When the corresponding SR bit is
set to logic [1], the output switching time is divided by 2 for the
dedicated output.
35XS3500
Analog Integrated Circuit Device Data ?
28
Freescale Semiconductor
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